1. Field of the Invention
The present invention relates to a semiconductor device which includes a field effect transistor having a LOCOS (local oxidation-of-silicon) offset for high voltage operation, and to a manufacturing method for the semiconductor device.
2. Description of the Related Art
Recent requirements from the market for integrated circuits (ICs), such as voltage regulators and switching regulators, which control a power supply voltage to obtain a constant voltage, have become diversified, seeking for, for example, an IC capable of ensuring safety operation even under a voltage range of 50 V or higher. As a field effect transistor (hereinafter referred to as a MOS (metal-oxide semiconductor) transistor) to be used in ICs for high voltage operation, there is known a MOS transistor with a LOCOS offset drain structure as an example of a conventional planar MOS transistor for high voltage operation.
FIGS. 3A to 3C illustrate a manufacturing method for a LOCOS offset MOS transistor. As illustrated in FIG. 3A, a sacrificial oxide film 22 and a nitride film 21 are deposited on a P-type silicon substrate, the nitride film 21 is selectively removed using photoresist as a mask, which is patterned to have an openings for a target region thereof, and an N-type offset diffusion layer 31 is formed through ion implantation. Next, as illustrated in FIG. 3B, using the nitride film 21 as a pattern, a LOCOS oxide film 23 is selectively formed through, for example, wet oxidation. Then, the nitride film 21 and the sacrificial oxide film 22 are removed to form a gate oxide film 24, and, for example, a polycrystalline silicon film is deposited on the gate oxide film 24. The polycrystalline silicon film is removed using photoresist as a mask, which is patterned to have an opening for a target region thereof, thereby forming a gate electrode 25. An N-type drain diffusion layer 34 and an N-type source diffusion layer 35 are formed through ion implantation using photoresist as a mask, which is patterned to have an opening for a target region thereof, thereby obtaining the structure of FIG. 3C.
According to the conventional structure illustrated in FIG. 3C, electric field relaxation between the gate electrode and the drain diffusion layer can be enhanced to achieve high voltage operation by appropriately setting a thickness of the LOCOS oxide film 23 and a concentration of the offset diffusion layer 31. However, in a junction portion between the offset diffusion layer 31 and the drain diffusion layer 34, the offset diffusion layer 31 cannot sufficiently cover a lower edge 34a of the drain diffusion layer 34 due to fluctuations in thickness of the LOCOS oxide film 23 and the nitride film 21 caused during the manufacturing process, resulting in a structure insufficient to relax electric field concentration on the lower edge 34a of the drain diffusion layer 34. For example, when the concentration of the offset diffusion layer 31 is set sufficiently high and the offset diffusion layer 31 is diffused up to the lower edge 34a of the drain diffusion layer 34, a depletion layer cannot extend from the offset diffusion layer 31, with the result that the electric field between the gate electrode and the drain diffusion layer enhances, becoming a factor for causing avalanche breakdown at a relatively low voltage. In the device design of such a high voltage operation element operative at 50 V, it becomes difficult to adopt the above-mentioned structure.
A countermeasure against the problem described above is disclosed in JP 06-29313 A, proposing a method in which a trench is formed in an offset portion of a LOCOS offset MOS transistor, an offset diffusion layer is formed therein, and a LOCOS oxide film fills the trench, whereby an electric field concentration region of a heavily-doped drain layer is covered with an aid of the offset diffusion.
According to the structure of the MOS transistor disclosed in JP 06-29313 A, an effective width of the offset diffusion layer increases, whereby a resistance component increases to lower the drivability of the MOS transistor. Further, the recess portion into which the LOCOS oxide film is embedded has a shape that flares toward the bottom. Accordingly, the offset diffusion layer also has a structure that flares toward the bottom, and the diffusion layer is structured to extend also in a channel direction of the MOS transistor. Accordingly, in order to prevent a leakage current flow due to the punch through phenomenon that occurs when a high voltage is applied to the drain electrode so that a depletion layer generated between the drain offset diffusion layer and a substrate makes a contact with a depletion layer of a source diffusion layer side, it is necessary to set a gate length of the MOS transistor larger. This condition is significant particularly in a case where both of the drain electrode and a source electrode are required to have a high withstanding voltage, which significantly affects its manufacturing cost due to increase in size.
Above all, according to the conventional structure, the withstanding voltage between the gate electrode and the drain electrode varies due to manufacturing fluctuation during the formation of the recess portion for the offset region and during the formation of the LOCOS oxide film filling the recess portion. For example, if the recess portion is formed deeper due to the manufacturing fluctuation and the LOCOS oxide film grows thinner, a channel end portion of the offset diffusion layer has a shape with sharp corners, with the result that the withstanding voltage is extremely deteriorated because the electric field concentration occurs. Accordingly, taking the manufacturing fluctuation into account, it is extremely difficult to ensure high voltage operation with the above-mentioned structure.